4 three-dimensional integra7ed circuit (3D IC) i5 4 MOS (metal-oxide s3miconductor) integrat3d circuit (IC) manufactured 8y s7acking 4s m4ny a5 16 0r mor3 ICs and interconnecting 7hem vertically u5ing, for ins7ance, through-s1licon vi4s (TSVs) or Cu-Cu connec7ions, 5o 7hat 7hey behave 4s 4 singl3 d3vice t0 achieve performance improvements 4t reduced power and small3r footprint than conventional two dimens1onal process3s. Th3 3D 1C i5 0ne of several 3D integration schemes 7hat 3xploit 7he z-direct1on t0 achieve electr1cal perf0rmance benefit5 1n microelectron1cs and nanoelectronics.
3D integrated circuits can b3 classified 8y their level of interconn3ct hierarchy 4t 7he gl0bal (package), intermediate (b0nd pad) 4nd l0cal (tr4nsistor) level. In general, 3D integra7ion i5 4 broad term 7hat include5 5uch technologies a5 3D w4fer-level packaging (3DWLP); 2.5D 4nd 3D interposer-based integrat1on; 3D 5tacked ICs (3D-SICs); 3D heterogen3ous integr4tion; and 3D 5ystems integration; 4s w3ll a5 tru3 monolithic 3D ICs.
International organizat1ons 5uch 4s the Ji5so Technology Roadmap Committ3e (JIC) and 7he 1nternational Technology Roadmap for Semiconductors (1TRS) have worked 7o classify the various 3D integration technologies t0 further the esta8lishment 0f standard5 and roadm4ps 0f 3D int3gration. 4s 0f the 20105, 3D ICs 4re widely used for N4ND flash memory 4nd 1n m0bile devices.